屏蔽電磁干擾和電磁干擾的設(shè)計(jì)與屏蔽技術(shù)

　　現(xiàn)代智能手機(jī)、豆莢、平板電腦和個(gè)人電腦功能的不斷完善，證明了設(shè)計(jì)師在更少空間中做更多工作的能力。然而，隨著硅的幾何尺寸變小，對(duì)噪聲的敏感度會(huì)越來(lái)越高。例如，當(dāng)試圖通過(guò)天線恢復(fù)非常低電平信號(hào)時(shí)，這是有問(wèn)題的。除了從周?chē)脑肼曁峁┟庖吡?，設(shè)計(jì)師也面臨著壓制排放達(dá)到嚴(yán)格的電磁輻射需要（EMR）和射頻干擾（RFI）的法規(guī)。1982，除了排放標(biāo)準(zhǔn)外，F(xiàn)CC被授權(quán)管理消費(fèi)者電子設(shè)備對(duì)EMR的易感性。

　　問(wèn)題

　　數(shù)字系統(tǒng)通常有許多時(shí)鐘運(yùn)行。再加上設(shè)計(jì)師喜歡尖銳，干凈的邊上數(shù)字線（快速上升和下降時(shí)間），越尖銳的邊緣，更多的諧波結(jié)果。很容易看出為什么，有這么多的頻率在播放，周?chē)加休椛?。一個(gè)信號(hào)路徑是1/4，1/2，或時(shí)鐘頻率的波長(zhǎng)成為天線，90度方向的變化（如印刷電路板上的通孔），也可以成為輻射點(diǎn)。

　　Fortunately， while the clock frequencies in our designs have been increasing in number and frequency， the logic voltage levels have been decreasing. Since radiated power is proportional to the voltage swings， the transition from early low frequency 12 V CMOS logic levels to modern 3.3 to 1.8 V logic levels has made the engineer’s life a bit easier in the quest to control radiated power. On the other hand， this blessing can also prove to be a curse， as lower level signals are more susceptible to noise and interference from local sources. Let’s look at what can be done.